The present invention relates generally to computer systems, and more specifically, to absolute address branching in a fixed-width reduced instruction set computing architecture.
In a computer system with a reduced instruction set computing (RISC) architecture, higher performance is achieved based on instruction simplicity to increase instruction execution rate. A RISC architecture typically includes a smaller optimized instruction set rather than a large number of specialized instructions that may be implemented in a complex instruction set computing (CISC) architecture. For RISC and CISC instructions, each instruction word typically includes an operation code (op-code) and one or more operands. One characteristic of a CISC architecture includes support for variable length instruction words. For example, a CISC architecture may include 32-bit instruction words, 48-bit instruction words, 64-bit instruction words, 80-bit instruction words, and the like. In contrast, RISC instruction words typically have a fixed instruction word width, such as 32 bits. A CISC architecture typically also supports a larger number of registers, includes complex addressing modes, and may require dozens of cycles to execute a single instruction.
A variety of branch instruction types may be defined in a RISC architecture as different branch instruction word formats. For instance, a displacement branch instruction adds a specified displacement defined in a displacement branch instruction word to the address of the displacement branch instruction. An absolute address branch instruction uses an absolute address included in an absolute address branch instruction word as an absolute address branch target address and pads remaining address bits with zeroes. A number of register-based branch instructions can also be defined where one or more registers are identified in a register-based branch instruction word, and values in the one or more registers are used to compute a branch target address. Typically, in a RISC architecture, branches that span a large address range employ register-based branch instructions, while branches that span a shorter address range or target a lower address range can employ a displacement or absolute address branch instruction. The fixed instruction word width in a RISC architecture can limit the number of address bits available for a displacement or absolute address branch instruction to the instruction word width less an op-code size.